Characterize Next-generation Receivers and Transmitters
The N4877A Clock Data Recovery is designed to operate over from 50 Mb/s to 32 Gb/s. The wide data rate range allows testing of emerging standards like 100GbE and 32GFC while covering existing lower speed standards. The 16G option operating up to 16.5 Gb/s is ideal for 16GFC as well as computer standards like USB 3.0, SATA, SAS and PCIe including PCIe gen4.
Recover Clocks or Clean-Up Clocks
The N4877A provides necessary clock signals for BERTs or oscilloscopes when access to appropriate clock signals from the device under test (DUT) is not possible. The N4877A recovers clocks from data streams if a clock is not available or can act as clean-up PLL for existing clocks with excessive intrinsic jitter to allow accurate measurements.
Simplify Receiver Testing of high speed Devices
The N4877A Clock Data Recovery and Demultiplexer 1:2 is the counterpart to the N4876A Multiplexer 2:1 and complements Keysight's J-BERT and ParBERT based receiver test solutions for data rates between 12.5 Gb/s and 28.4 Gb/s.
SW controlled swappable demultiplexer outputs, a Jitter Tolerance Test mode and connection cable kits specially designed for J-BERT N4903B simplify receiver testing.
Measure the real Performance of clock less Devices
Low intrinsic jitter paired with tunable loop bandwidth, selectable peaking and high sensitivity enable accurate measurements of transmitters.
The N4877A’s auxiliary clock output provides ultralow intrinsic random jitter of less than a 100 fs rms making it the ideal companion for sampling scopes equipped with a precision timebase.
Easily Control all Settings
The settings of the N4877A Clock Data Recovery and Demultiplexer can be controlled through its rear-panel USB connection and a standalone user interface that runs on a Windows® PC. The SW can be installed on instruments running Windows® XP or Windows® 7
PLL and Jitter Spectrum Analysis
Us e 86100CU-400 or 86100DU-400 software to make fast, accurate and repeatable measurements of phase-locked loop (PLL) bandwidth/jitter transfer. With a precision jitter source a clock data recovery (N4877A, 83496B or N1070A) can be configured as a jitter receiver to create a PLL stimulus-response test system.