The DDR3 DRAM BGA probe enables logic analyzer state and timing measurements of all the DRAM buses, including the DQ, DQS, and clock signals of x4, x8 and x16 DRAMs using the JEDEC standard common DDR3 DRAM footprint.
The probe interposes between the DRAM being probed and the PC board where the DRAM would normally be soldered.
The probe is designed to be soldered to the PCB footprint for the DRAM The DRAM being probed is then soldered to the top side of the probe.
Each DRAM signal in the common footprint (including those defined for x4, x8 and x16 DRAMs) passes directly from the bottom side of the probe to the top side of the probe. Buried probe resistors placed at the DRAM balls connect the probed signals to the rigid flex to mate with an Agilent cable adapter (ZIF probe).